An efficient approach to simultaneous transistor and interconnect sizing
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Optimal wire and transistor sizing for circuits with non-tree topology
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Migration: a new technique to improve synthesized designs through incremental customization
DAC '98 Proceedings of the 35th annual Design Automation Conference
Macro-driven circuit design methodology for high-performance datapaths
Proceedings of the 37th Annual Design Automation Conference
Checkpointing and Its Applications
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Gate sizing by Lagrangian relaxation revisited
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
An optimal algorithm for sizing sequential circuits for industrial library based designs
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Gate sizing by Lagrangian relaxation revisited
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Approximation scheme for restricted discrete gate sizing targeting delay minimization
Journal of Combinatorial Optimization
An efficient algorithm for library-based cell-type selection in high-performance low-power designs
Proceedings of the International Conference on Computer-Aided Design
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A standard cell library typically contains several versions of any given gate type, each of which has a different gate size. We consider the problem of choosing optimal gate sizes from the library to minimize a cost function (such as total circuit area) while meeting the timing constraints imposed on the circuit. After presenting an efficient algorithm for combinational circuits, we examine the problem of minimizing the area of a synchronous sequential circuit for a given clock period specification. This is done by appropriately selecting a size for each gate in the circuit from a standard-cell library, and by adjusting the delays between the central clock distribution node and individual flip-flops. Experimental results show that by formulating gate size selection together with the clock skew optimization as a single optimization problem, it is not only possible to reduce the optimized circuit area, but also to achieve faster clocking frequencies. Finally, we address the problem of making this work applicable to very large synchronous sequential circuits by partitioning these circuits to reduce the computational complexity