Predicting conditional branch directions from previous runs of a program
ASPLOS V Proceedings of the fifth international conference on Architectural support for programming languages and operating systems
A survey of power estimation techniques in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Energy characterization based on clustering
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Power macromodeling for high level power estimation
DAC '97 Proceedings of the 34th annual Design Automation Conference
High-level power modeling, estimation, and optimization
DAC '97 Proceedings of the 34th annual Design Automation Conference
The SimpleScalar tool set, version 2.0
ACM SIGARCH Computer Architecture News
A framework for estimation and minimizing energy dissipation of embedded HW/SW systems
DAC '98 Proceedings of the 35th annual Design Automation Conference
Reducing power in high-performance microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
Pipeline gating: speculation control for energy reduction
Proceedings of the 25th annual international symposium on Computer architecture
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Cycle-accurate macro-models for RT-level power analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An architectural solution for the inductive noise problem due to clock-gating
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Energy-driven integrated hardware-software optimizations using SimplePower
Proceedings of the 27th annual international symposium on Computer architecture
TEM2P2EST: A Thermal Enabled Multi-model Power/Performance ESTimator
PACS '00 Proceedings of the First International Workshop on Power-Aware Computer Systems-Revised Papers
Inductive Noise Reduction at the Architectural Level
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Analysis of Ground Bounce in Deep Sub-Micron Circuits
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
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Because the inductive noise Ldi/dt is induced by the power change and can have disastrous impact on the timing and reliability of the system, high-performance CPU designs are more concerned with the step power reduction instead of the average power reduction. The step power is defined as the power difference between the previous and present clock cycles, and represents the Ldi/dt noise at the microarchitecture level. Two mechanisms at the microarchitecture level are proposed in this paper to reduce the step power of the floating point unit (FPU), as FPU is the potential "hot" spot of Ldi/dt noise. The two mechanisms, ramping up and ramping down FPU based on instruction fetch queue (IFQ) scanning and PC+N instruction prediction, can meet any specific step power constraint. We implement and evaluate the two mechanisms using a performance and power simulator based on the SimpleScalar toolset. Experiments using SPEC95 benchmarks show that our method reduces the performance loss by a factor of four when compared to a recent work.