Assigning confidence to conditional branch predictions
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
Exceeding the dataflow limit via value prediction
Proceedings of the 29th annual ACM/IEEE international symposium on Microarchitecture
The filter cache: an energy efficient memory structure
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Confidence estimation for speculation control
Proceedings of the 25th annual international symposium on Computer architecture
Pipeline gating: speculation control for energy reduction
Proceedings of the 25th annual international symposium on Computer architecture
Branch Target Buffer Design and Optimization
IEEE Transactions on Computers
Very low power pipelines using significance compression
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Automated design of finite state machine predictors for customized processors
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Ramp Up/Down Functional Unit to Reduce Step Power
PACS '00 Proceedings of the First International Workshop on Power-Aware Computer Systems-Revised Papers
Integrated I-cache Way Predictor and Branch Target Buffer to Reduce Energy Consumption
ISHPC '02 Proceedings of the 4th International Symposium on High Performance Computing
Cost-Efficient Branch Target Buffers
Euro-Par '00 Proceedings from the 6th International Euro-Par Conference on Parallel Processing
Minimizing Energy Consumption for High-Performance Processing
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Instruction Prediction for Step Power Reduction
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Power modeling and reduction of VLIW processors
Compilers and operating systems for low power
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This paper proposes a micro-architectural technique in which a prediction is made for some power-hungry units of a processor. The prediction consists of whether the result of a particular unit or block of logic will be useful in order to execute the current instruction. If it is predicted useless, then that block is disabled.It would be ideal if the predictions were totally accurate, thus not decreasing the instruction-per-cycle (IPC) performance metric. However, this is not the case: the IPC might be degraded which in turn may offset the power savings obtained with the predictors due to the extra cycles to complete the execution of the application being run on the processor.In general, some logic may determine which of the block(s) that have a predictor associated will be disabled based on the outcome of the predictors and possibly some other signals from the processor. The overall processor power consumption reduction is a function of how accurate the predictors are, what percentage of the total processor power consumption corresponds to the blocks being predicted, and how sensitive to the IPC the different blocks are.A case example is presented where two blocks are predicted for low power: the on-chip L2 cache for instruction fetches, and the Branch Target Buffer. The IPC vs power-consumption design space is explored for a particular micro-processor architecture. Both the average and the peak power consumption are targeted. Although the power analysis is beyond the scope of this paper, high-level estimations are done to show that it is plausible that the ideas described might produce a significant reduction in useless block accesses. Clearly, this reduction may be exploited to reduce the power consumption demands of high-performance processors.