Power modeling and reduction of VLIW processors

Authors:
Weiping Liao;Lei He
Affiliations:
Electrical Engineering Department, University of California, Los Angeles, CA;Electrical Engineering Department, University of California, Los Angeles, CA
Venue:
Compilers and operating systems for low power
Year:
2003

Citing 11
Cited 2

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Abstract

In this chapter, we first present a cycle-accurate power simulator based on the IMPACT toolset. This simulator allows a designer to evaluate both VLIW compiler and micro-architecture innovations for power reduction. Using this simulator, we then develop and compare the following techniques with a bounded performance loss of 1% compared to the case without any dynamic throttling: (i) clock ramping with hardware-based prescan (CRHP), and (ii) clock ramping with compiler-based prediction (CRCP). Experiments using SPEC2000 floating point benchmarks show that the power consumed by floating point units can be reduced by up to 31% and 37%, in CRHP and CRCP respectively.