A methodology to analyze power, voltage drop and their effects on clock skew/delay in early stages of design

  • Authors:

  • Masato Iwabuchi;Noboru Sakamoto;Yasushi Sekine;Takashi Omachi

  • Affiliations:

  • Hitachi, Ltd., 6-16-3 Shinmachi, Ome, Tokyo 198-8512, Japan;Hitachi, Ltd., 6-16-3 Shinmachi, Ome, Tokyo 198-8512, Japan;Hitachi, Ltd., 6-16-3 Shinmachi, Ome, Tokyo 198-8512, Japan;Hitachi, Ltd., 6-16-3 Shinmachi, Ome, Tokyo 198-8512, Japan

  • Venue:
  • ISPD '99 Proceedings of the 1999 international symposium on Physical design
  • Year:
  • 1999

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Abstract