Reducing power in high-performance microprocessors
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To provide higher performance by staying within a constant power budget is challenging. Today, operational cost and specifically energy cost constitute a large portion of an organization's Total Cost of Ownership (TCO), so it is crucial that microprocessor consumes the lowest possible power for a given workload. In this paper, we describe the major challenges faced by the microprocessor architects in achieving higher performance within constant power budget or energy-efficiency, with special focus on design technologies and solutions. We present a die level power simulation solution that facilitates exploration of system-level power management algorithms that budget power for various microprocessor die components. We demonstrate usage methodology via real-life use case studies and recommend future areas of research that can enhance the proposed power management simulation methodology.