Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
Experiences using the ParaScope Editor: an interactive parallel programming tool
PPOPP '93 Proceedings of the fourth ACM SIGPLAN symposium on Principles and practice of parallel programming
Generating schedules and code within a unified reordering transformation framework
Generating schedules and code within a unified reordering transformation framework
Power analysis of embedded software: a first step towards software power minimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Low-power architectural design methodologies
Low-power architectural design methodologies
Power exploration for data dominated video applications
ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design
Allocation of multiport memories for hierarchical data stream
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Analytical energy dissipation models for low-power caches
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
System-level synthesis of low-power hard real-time systems
DAC '97 Proceedings of the 34th annual Design Automation Conference
Reducing power in high-performance microprocessors
DAC '98 Proceedings of the 35th annual Design Automation Conference
System-Level Power Optimization of Video Codecs on Embedded Cores: A Systematic Approach
Journal of VLSI Signal Processing Systems - Special issue on future directions in the design and implementations of DSP systems
Proceedings of the conference on Design, automation and test in Europe
Digital Signal Processing
Image and Video Compression Standards: Algorithms and Architectures
Image and Video Compression Standards: Algorithms and Architectures
Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design
Memory Issues in Embedded Systems-on-Chip: Optimizations and Exploration
Memory Issues in Embedded Systems-on-Chip: Optimizations and Exploration
Power Aware Design Methodologies
Power Aware Design Methodologies
Hardware Cache Optimization for Parallel Multimedia Applications
Euro-Par '98 Proceedings of the 4th International Euro-Par Conference on Parallel Processing
System level memory optimization for hardware-software co-design
CODES '97 Proceedings of the 5th International Workshop on Hardware/Software Co-Design
SCALP: an iterative-improvement-based low-power data path synthesis system
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper the important issues in mapping data dominated multimedia applications on Very Long Instruction Word (VLIW) multimedia processors are addressed. The main design quality factors of applications realized on the target architecture platform are presented and their interactions are explored. Power consumption is the major cost factor while performance is the overriding constraint in realizations of multimedia applications on the target architecture platform. A methodology for the reduction of the data transfer and storage related power consumption, which forms an important part of the total power budget of the system, and the execution time of applications realized on VLIW multimedia processors, has been developed. The methodology is based on the application of a number of transformations, mainly oriented towards data transfer and storage optimization, to a high level description of the target application. The main focus of this paper is on the interaction of the proposed code transformations with the exploitation of subword parallelism (for example through the application of special performance improving arithmetic subword instructions present in modern VLIW multimedia processors). Experimental results from real-life data-dominated multimedia applications clearly demonstrate that the application of the proposed transformations is orthogonal to the exploitation of subword parallelism. A second conclusion is that the positive impact of the proposed code transformations on performance is typically even larger than the effect of the subword parallelism exploitation for the complete application. The effect of the subword parallelism exploitation is even enhanced after the application of the proposed code transformations.