A VLIW architecture for a trace Scheduling Compiler
IEEE Transactions on Computers - Special issue on architectural support for programming languages and operating systems
The multiscalar architecture
Improving superscalar instruction dispatch and issue by exploiting dynamic code sequences
Proceedings of the 24th annual international symposium on Computer architecture
Complexity-effective superscalar processors
Proceedings of the 24th annual international symposium on Computer architecture
The energy complexity of register files
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
IEEE Micro
The Alpha 21264 Microprocessor
IEEE Micro
Inherently lower-power high-performance superscalar architectures
Inherently lower-power high-performance superscalar architectures
Power aware microarchitecture resource scaling
Proceedings of the conference on Design, automation and test in Europe
Inherently Lower-Power High-Performance Superscalar Architectures
IEEE Transactions on Computers
Unified architecture level energy-efficiency metric
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Proceedings of the 2002 international symposium on Low power electronics and design
Energy-efficient hybrid wakeup logic
Proceedings of the 2002 international symposium on Low power electronics and design
Application-driven processor design exploration for power-performance trade-off analysis
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Microarchitecture-level power management
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
An innovative low-power high-performance programmable signal processor for digital communications
IBM Journal of Research and Development
Balancing hardware intensity in microprocessor pipelines
IBM Journal of Research and Development
Dynamic Resizing of Superscalar Datapath Components for Energy Efficiency
IEEE Transactions on Computers
SEED: scalable, efficient enforcement of dependences
Proceedings of the 15th international conference on Parallel architectures and compilation techniques
Trends toward on-chip networked microsystems
International Journal of High Performance Computing and Networking
Strategies for mapping dataflow blocks to distributed hardware
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Energy and performance evaluation of lossless file data compression on server systems
SYSTOR '09 Proceedings of SYSTOR 2009: The Israeli Experimental Systems Conference
Architecture level design space exploration of superscalar processor for multimedia applications
SPECTS'09 Proceedings of the 12th international conference on Symposium on Performance Evaluation of Computer & Telecommunication Systems
The challenges of massive on-chip concurrency
ACSAC'05 Proceedings of the 10th Asia-Pacific conference on Advances in Computer Systems Architecture
Improving coherence protocol reactiveness by trading bandwidth for latency
Proceedings of the 9th conference on Computing Frontiers
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In recent years reducing power has become a critical design goal for high-performance microprocessors. This work attempts to bring the power issue to the earliest phase of high-performance microprocessor development. We propose a methodology for power-optimization at the micro-architectural level. First, major targets for power reduction are identified within superscalar microarchitecture, then an optimization of a superscalar micro-architecture is performed that generates a set of energy-efficient configurations forming a convex hull in the power-performance space. The energy-efficient families are then compared to find configurations that dissipate the lowest power given a performance target, or, conversely, deliver the highest performance given a power budget. Application of the developed methodology to a superscalar micro-architecture shows that at the architectural level there is a potential for reducing power up to 50%, given a performance requirement, and for up to 15% performance improvement, given a power budget.