Architectural Considerations for Energy Efficiency

Authors:
Hoang Q. Dao;Bart R. Zeydel;Vojin G. Oklobdija
Affiliations:
Advanced Computer Systems Engineering Laboratory Department of Electrical and Computer Engineering, University of California, Davis, CA;Advanced Computer Systems Engineering Laboratory Department of Electrical and Computer Engineering, University of California, Davis, CA;Advanced Computer Systems Engineering Laboratory Department of Electrical and Computer Engineering, University of California, Davis, CA
Venue:
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Year:
2005

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Abstract

The formal analysis of parallelism and pipelining is performed on an 8-bit Add-Compare-Select element of a Viterbi decoder. The results are quantified through a study of the delay and energy behaviors of gates and complex circuits due to supply scaling and circuit optimization on a modified test setup accounting for routing cost. The energy-throughput relationships of both pipelining and parallelism are characterized in connection to their corresponding depth and degree, showing clear advantages of pipelining over parallelism.