A minimum total power methodology for projecting limits on CMOS GSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Dynamic voltage scaling on a low-power microprocessor
Proceedings of the 7th annual international conference on Mobile computing and networking
Low Voltage Low Power CMOS Design Techniques for Deep Submicron ICs
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Leakage Current Reduction in Sequential Circuits by Modifying the Scan Chains
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Voltage setup problem for embedded systems with multiple voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The limit of dynamic voltage scaling and insomniac dynamic voltage scaling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy-Efficient Real-Time Task Scheduling in Multiprocessor DVS Systems
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Static task-scheduling algorithms for battery-powered DVS systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Temperature and supply Voltage aware performance and power modeling at microarchitecture level
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper the utilization of neural processors as supervisory units that control predictive techniques of dynamic power management is described. Power management becomes more and more important as density of power dissipated in modern integrated circuits, especially microprocessors, continuously raises and can be even higher than 4 megawatts per square meter. It causes temperature increases that might be dangerous for the chip. The presented supervisors that are based on neurons allow correct prediction of chip temperature on the basis of current temperature, power losses that will be consumed in the next units of time, as well as previous power dissipations. Their task is to keep the throughput of high-frequency and high-efficiency systems on the highest possible level under the conditions of energy savings and maintaining safe temperature of chip. The supervisory units are designed using 32-bit and fixed-point precision.