Transistor sizing issues and tool for multi-threshold CMOS technology
DAC '97 Proceedings of the 34th annual Design Automation Conference
MTCMOS hierarchical sizing based on mutual exclusive discharge patterns
DAC '98 Proceedings of the 35th annual Design Automation Conference
Leakage current in low standby power and high performance devices: trends and challenges
Proceedings of the 2002 international symposium on Physical design
Proceedings of the 39th annual Design Automation Conference
Sub-90nm technologies: challenges and opportunities for CAD
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Understanding and minimizing ground bounce during mode transition of power gating structures
Proceedings of the 2003 international symposium on Low power electronics and design
Post-layout leakage power minimization based on distributed sleep transistor insertion
Proceedings of the 2004 international symposium on Low power electronics and design
Distributed sleep transistor network for power reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leakage control through fine-grained placement and sizing of sleep transistors
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
GORDIAN: VLSI placement by quadratic programming and slicing optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design and optimization of multithreshold CMOS (MTCMOS) circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Multi-threshold CMOS (MTCMOS) technology is an effective sub-threshold leakage power reduction method in CMOS circuits, which satisfies high-performance and low-power design requirements. The optimization of virtual supply network plays an important role in MTCMOS low-power design. Existing low-power works are mainly on gate level, without any optimization on physical design level, which can lead to a large amount of virtual supply networks. Merging the objective of virtual networks minimization into physical design, this paper presents (1) a low-power-driven physical design flow; (2) a novel low-power placement to simultaneously place standard cells and sleep transistors; and (3) the sleep transistor relocation technique to further reduce the virtual supply networks. Experimental results are promising for both achieving up to 28.15% savings for virtual supply networks and well controlling the increase of signal nets.