Leakage current in low standby power and high performance devices: trends and challenges

  • Authors:

  • Geoffrey C-F Yeap

  • Affiliations:

  • Motorola Inc., Austin, TX

  • Venue:
  • Proceedings of the 2002 international symposium on Physical design
  • Year:
  • 2002

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Abstract

IC technology is continuing to scale according to Moore's Law, with the overall chip circuit requirements driving the MOSFET device and process integration requirements and optimal choices. In the 2001 International Technology Roadmap for Semiconductors (ITRS) [1] the driver for the high performance logic is maximizing MOSFET intrinsic speed, while the driver for low standby power logic is minimizing MOSFET leakage current. Total leakage current of a MOSFET consists of three components: off-state sub-threshold leakage current, gate direct tunneling leakage current and source/drain junction leakage current. In this paper, trends and challenges for each leakage current component in low standby power and high performance devices are discussed from the perspective of the 2001 ITRS and recently reported literatures.