Current density aware power switch placement algorithm for power gating designs

Authors:
Jai-Ming Lin;Che-Chun Lin;Zong-Wei Syu;Chih-Chung Tsai;Kevin Huang
Affiliations:
Department of Electrical Engineering, National Cheng Kung University, Tainan 70101, Taiwan Roc;Department of Electrical Engineering, National Cheng Kung University, Tainan 70101, Taiwan Roc;Department of Electrical Engineering, National Cheng Kung University, Tainan 70101, Taiwan Roc;Himax Technologies, Inc., Tainan 74148, Taiwan Roc;Himax Technologies, Inc., Tainan 74148, Taiwan Roc
Venue:
Proceedings of the 2014 on International symposium on physical design
Year:
2014

Citing 10
Cited 0

MTCMOS hierarchical sizing based on mutual exclusive discharge patterns

DAC '98 Proceedings of the 35th annual Design Automation Conference
Life is CMOS: why chase the life after?

Proceedings of the 39th annual Design Automation Conference
Dynamic and leakage power reduction in MTCMOS circuits using an automated efficient gate clustering technique

Proceedings of the 39th annual Design Automation Conference
Distributed sleep transistor network for power reduction

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Benefits and Costs of Power-Gating Technique

ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Leakage control through fine-grained placement and sizing of sleep transistors

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Functionality directed clustering for low power MTCMOS design

Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A Power Network Synthesis Method for Industrial Power Gating Designs

ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Power-switch routing for coarse-grain MTCMOS technologies

Proceedings of the 2009 International Conference on Computer-Aided Design
Power-up sequence control for MTCMOS designs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

Due to advances in manufacture technology, leakage current increases dramatically in modern ICs. Power gating technique is an efficient and effective method to resolve this problem. In order to turn off supply voltage in a low-power domain, it has to insert power switches into designs. However, chip area and IR-drop of circuits are impacted by the number and locations of inserted power switches. Unlike previous works using greedy algorithm to handle this problem, this paper proposes a simple model to approximate the equivalent resistance of power switches in a low-power domain, and uses the binary search method to get the precise value. Based on this value, power switches are allocated by a partition-based approach. Experimental results demonstrate that our approach can insert less number of power switches and still satisfy the IR-drop constraint than other approaches. Moreover, this method is very efficient.