Transistor sizing issues and tool for multi-threshold CMOS technology
DAC '97 Proceedings of the 34th annual Design Automation Conference
MTCMOS hierarchical sizing based on mutual exclusive discharge patterns
DAC '98 Proceedings of the 35th annual Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
Distributed sleep transistor network for power reduction
Proceedings of the 40th annual Design Automation Conference
Understanding and minimizing ground bounce during mode transition of power gating structures
Proceedings of the 2003 international symposium on Low power electronics and design
Wake-up protocols for controlling current surges in MTCMOS-based technology
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
DFM/DFY practices during physical designs for timing, signal integrity, and power
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
An efficient wake-up schedule during power mode transition considering spurious glitches phenomenon
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Experiences of low power design implementation and verification
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Power gating scheduling for power/ground noise reduction
Proceedings of the 45th annual Design Automation Conference
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Design of a flexible reactivation cell for safe power-mode transition in power-gated circuits
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Power-switch routing for coarse-grain MTCMOS technologies
Proceedings of the 2009 International Conference on Computer-Aided Design
An efficient wake-up strategy considering spurious glitches phenomenon for power gating designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Ground-bouncing-noise-aware combinational MTCMOS circuits
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Current density aware power switch placement algorithm for power gating designs
Proceedings of the 2014 on International symposium on physical design
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Power gating is effective for reducing standby leakage power asmulti-threshold CMOS (MTCMOS) designs have become popular in the industry. However, a large inrush current and dynamic IR drop may occur when a circuit domain is powered up with MTCMOS switches. This could in turn lead to improper circuit operation. We propose a novel framework for generating a proper power-up sequence of the switches to control the inrush current of a power-gated domain while minimizing the power-up time and reducing the dynamic IR drop of the active domains. We also propose a configurable domino-delay circuit for implementing the sequence. Experimental results based on state-of-the-art industrial designs demonstrate the effectiveness of the proposed framework in limiting the inrush current, minimizing the power-up time, and reducing the dynamic IR drop. Results further confirm the efficiency of the framework in handling large-scale designs with more than 80 K power switches and 100 M transistors.