Design considerations and tools for low-voltage digital system design
DAC '96 Proceedings of the 33rd annual Design Automation Conference
COSMOS: a continuous optimization approach for maximum power estimation of CMOS circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Understanding and minimizing ground bounce during mode transition of power gating structures
Proceedings of the 2003 international symposium on Low power electronics and design
Decoupling capacitance allocation and its application to power-supply noise-aware floorplanning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimal decoupling capacitor sizing and placement for standard-cell layout designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Power gating scheduling for power/ground noise reduction
Proceedings of the 45th annual Design Automation Conference
Power-up sequence control for MTCMOS designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper proposes strategies to control the wake-up noise for circuits implemented in MTCMOS technology. In MTCMOS circuits, during the switchings between the active and standby modes, sudden surges in current happens due to floating voltages at the nodes. These surges might violate the reliability of the circuit. In this paper we address the above problem by developing wake-up strategies to control these current surges as the circuit is getting turned on. Through gradually turning on a circuit a smaller current will be drawn from the power-grid network. A novel partitioning technique is proposed for MTCMOS circuits under a given constraint of maximum drawn-current from the power-grid network. Two approaches are proposed in this paper; the optimal ILP-based formulation and a polynomial-time heuristic. Experimental results show that up to 90.7% improvement in peak drawn-current is obtained with a maximum of 4 clock cycles time to turn on the circuit. Also result show the effectiveness of the heuristic in terms of the quality of solution and a run-time of up to 6600 times faster than the ILP approach for larger circuits.