Tools and methodologies for low power design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Benefits and Costs of Power-Gating Technique
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Power Gating with Multiple Sleep Modes
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Challenges in sleep transistor design and implementation in low-power designs
Proceedings of the 43rd annual Design Automation Conference
DFM/DFY practices during physical designs for timing, signal integrity, and power
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Efficient on-line module-level wake-up scheduling for high performance multi-module designs
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Verification work reduction methodology in low-power chip implementation
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
Open systemc simulator with support for power gating design
International Journal of Reconfigurable Computing - Special issue on Selected Papers from the Symposium on Integrated Circuits and Systems Design (SBCCI 2011)
Power-up sequence control for MTCMOS designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we present the experiences of some low power solutions that have been successfully implemented in 90nm/65nm production tape-outs. We also focus on power gating design, an effective low leakage solution, and present the experiences of power switch planning, optimization, and verification. Dynamic IR drop is an important issue in low power design, which may reduce the logic gate noise margins and result in functional or timing failures. We will present a low cost but effective methodology for dynamic IR drop prevention and fixing.