An open-source tool for simulation of partially reconfigurable systems using SystemC
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
Writing Testbenches using SystemVerilog
Writing Testbenches using SystemVerilog
Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies (Springer Series in Advanced Microelectronics)
Modelling and Simulation of Dynamic and Partially Reconfigurable Systems using SystemC
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Experiences of low power design implementation and verification
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Dedicated Rewriting: Automatic Verification of Low Power Transformations in RTL
VLSID '09 Proceedings of the 2009 22nd International Conference on VLSI Design
Low Power Methodology Manual: For System-on-Chip Design
Low Power Methodology Manual: For System-on-Chip Design
Functional verification of power gate design in SystemC RTL
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Functional verification of power gated designs by compositional reasoning
Formal Methods in System Design
FPGA Based Implementation of High Performance Architectural Level Low Power 32-bit RISC Core
ARTCOM '09 Proceedings of the 2009 International Conference on Advances in Recent Technologies in Communication and Computing
An efficient wakeup scheduling considering resource constraint for sensor-based power gating designs
Proceedings of the 2009 International Conference on Computer-Aided Design
An efficient wake-up strategy considering spurious glitches phenomenon for power gating designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and verification methods of Toshiba's wireless LAN baseband SoC
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
System Level Synthesis for Ultra Low-Power Wireless Sensor Nodes
DSD '10 Proceedings of the 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools
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Power gating is one of the most efficient power consumption reduction techniques. However, when applied in several different parts of a complex design, functional verification becomes a challenge. Lately, the verification process of this technique has been executed in a Register-Transfer Level (RTL) abstraction, based on the Common Power Format (CPF) and the Unified Power Format (UPF). The purpose of this paper is to present an OSCI SystemC simulator with support to the power gating design. This simulator is an alternative to assist the functional verification accomplishment of systems modeled in RTL. The possibility of controlling the retention and isolation of power gated functional block (PGFB) is presented in this work, turning the simulations more stable and accurate. Two case studies are presented to demonstrate the new features of that simulator.