Design and verification methods of Toshiba's wireless LAN baseband SoC

Authors:
Masanori Kuwahara
Affiliations:
Toshiba Corporation Semiconductor Company, Horikawa-Cho, Sawai-Ku, Kawasaki, Kanagawa
Venue:
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Year:
2010

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Abstract

This paper presents design and verification methods of Toshiba's wireless LAN (WLAN) baseband SoCs. An FPGA-based high-speed and reliable verification environment for physical layer (PHY), a new SDL-based hardware design method for media access control layer (MAC), and an ultra low power design resulting in power consumption of 22 uW in the deep-sleep mode are described.