Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies (Springer Series in Advanced Microelectronics)

Experimental study on body-biasing layout style-- negligible area overhead enables sufficient speed controllability --

Proceedings of the 18th ACM Great Lakes symposium on VLSI

Novel circuit technique for reduction of active drain current in low leakage digital VLSI circuits

Proceedings of the International Conference and Workshop on Emerging Trends in Technology

Power-gated MOS current mode logic (PG-MCML): a power aware DPA-resistant standard cell library

Proceedings of the 48th Design Automation Conference

Switching noise optimization in the wake-up phase of leakage-aware power gating structures

PATMOS'09 Proceedings of the 19th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation

A configurable architecture to limit wakeup current in dynamically-controlled power-gated FPGAs

Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays

A semiempirical model for wakeup time estimation in power-gated logic clusters

Proceedings of the 49th Annual Design Automation Conference

Open systemc simulator with support for power gating design

International Journal of Reconfigurable Computing - Special issue on Selected Papers from the Symposium on Integrated Circuits and Systems Design (SBCCI 2011)