Design flow instantiation for run-time reconfigurable systems: a case study
EURASIP Journal on Embedded Systems - Reconfigurable Computing and Hardware/Software Codesign
A Flexible system level design methodology targeting run-time reconfigurable FPGAs
EURASIP Journal on Embedded Systems - Reconfigurable Computing and Hardware/Software Codesign
Functional verification of power gate design in SystemC RTL
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
OSSS+R: a framework for application level modelling and synthesis of reconfigurable systems
Proceedings of the Conference on Design, Automation and Test in Europe
Journal of Systems Architecture: the EUROMICRO Journal
Modeling and implementation of a power estimation methodology for systemC
International Journal of Reconfigurable Computing - Special issue on Selected Papers from the Symposium on Integrated Circuits and Systems Design (SBCCI 2011)
Open systemc simulator with support for power gating design
International Journal of Reconfigurable Computing - Special issue on Selected Papers from the Symposium on Integrated Circuits and Systems Design (SBCCI 2011)
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The Scalable Communications Core (SCC) is a power- and area-efficient solution for physical layer (PHY) and lower MAC processing of concurrent multiple wireless protocols. Our architecture consists of coarse-grained, heterogeneous, programmable accelerators ...