Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
A power estimation methodology for systemC transaction level models
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Modelling and Simulation of Dynamic and Partially Reconfigurable Systems using SystemC
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
TLM Platform Based on SystemC for STARSoC Design Space Exploration
AHS '08 Proceedings of the 2008 NASA/ESA Conference on Adaptive Hardware and Systems
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Functional verification of power gate design in SystemC RTL
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Dynamic System Reconfiguration in Heterogeneous Platforms: The MORPHEUS Approach
Dynamic System Reconfiguration in Heterogeneous Platforms: The MORPHEUS Approach
A statistical power estimation methodology embedded in a SystemC code translator
Proceedings of the 24th symposium on Integrated circuits and systems design
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This work describes a methodology to model power consumption of logic modules. A detailed mathematical model is presented and incorporated in a tool for translation of models written in VHDL to SystemC. The functionality for implicit power monitoring and estimation is inserted at module translation. The translation further implements an approach to wrap RTL to TLM interfaces so that the translated module can be connected to a system-level simulator. The power analysis is based on a statistical model of the underlying HW structure and an analysis of input data. The flexibility of the C++ syntax is exploited, to integrate the power evaluation technique. The accuracy and speed-up of the approach are illustrated and compared to a conventional power analysis flow using PPR simulation, based on Xilinx technology.