A decade of reconfigurable computing: a visionary retrospective
Proceedings of the conference on Design, automation and test in Europe
Re-configurable computing in wireless
Proceedings of the 38th annual Design Automation Conference
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Mapping Applications onto Reconfigurable Kress Arrays
FPL '99 Proceedings of the 9th International Workshop on Field-Programmable Logic and Applications
MEMOCODE '03 Proceedings of the First ACM and IEEE International Conference on Formal Methods and Models for Co-Design
UML-based co-design for run-time reconfigurable architectures
Languages for system specification
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Implementing an OFDM Receiver on the RaPiD Reconfigurable Architecture
IEEE Transactions on Computers
Modeling and optimizing run-time reconfiguration using evolutionary computation
ACM Transactions on Embedded Computing Systems (TECS)
Proceedings of the 42nd annual Design Automation Conference
Support for partial run-time reconfiguration of platform FPGAs
Journal of Systems Architecture: the EUROMICRO Journal
Modelling and Simulation of Dynamic and Partially Reconfigurable Systems using SystemC
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Static scheduling techniques for dependent tasks on dynamically reconfigurable devices
Journal of Systems Architecture: the EUROMICRO Journal
EURASIP Journal on Applied Signal Processing
An overview of reconfigurable hardware in embedded systems
EURASIP Journal on Embedded Systems
EURASIP Journal on Applied Signal Processing
Design and implementation of MC-CDMA systems for future wireless networks
EURASIP Journal on Applied Signal Processing
High level modeling of dynamic reconfigurable FPGAs
International Journal of Reconfigurable Computing - Selected papers from ReCoSoc08
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Reconfigurable computing is certainly one of the most important emerging research topics on digital processing architectures over the last few years. The introduction of run-time reconfiguration (RTR) on FPGAs requires appropriate design flows and methodologies to fully exploit this new functionality. For that purpose, we present an automatic design generation methodology for heterogeneous architectures based on DSPs and FPGAs that ease and speed RTR implementation. We focus on how to take into account specificities of partially reconfigurable components from a high-level specification during the design generation steps. This method automatically generates designs for both fixed and partially reconfigurable parts of an FPGA with automatic management of the reconfiguration process. Furthermore, this automatic design generation enables a reconfiguration prefetching technique to minimize reconfiguration latency and buffer-merging techniques to minimize memory requirements of the generated design. This concept has been applied to different wireless access schemes, based on a combination of OFDM and CDMA techniques. This implementation example illustrates the benefits of the proposed design methodology.