Proceedings of the joint conference on Languages, compilers and tools for embedded systems: software and compilers for embedded systems
Component-based design approach for multicore SoCs
Proceedings of the 39th annual Design Automation Conference
UML-Based Analysis of Embedded Systems Using a Mapping to VHDL
HASE '99 The 4th IEEE International Symposium on High-Assurance Systems Engineering
Application of UML for hardware design based on design process model
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A Lightweight Approach for Embedded Reconfiguration of FPGAs
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Transaction level modelling of SCA compliant software defined radio waveforms and platforms PIM/PSM
Proceedings of the conference on Design, automation and test in Europe
A Flexible system level design methodology targeting run-time reconfigurable FPGAs
EURASIP Journal on Embedded Systems - Reconfigurable Computing and Hardware/Software Codesign
GePaRD - A High-Level Generation Flow for Partially Reconfigurable Designs
ISVLSI '08 Proceedings of the 2008 IEEE Computer Society Annual Symposium on VLSI
An adaptive system-on-chip for network applications
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
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As System-on-Chip (SoC) based embedded systems have become a defacto industry standard, their overall design complexity has increased exponentially in recent years, necessitating the introduction of new seamless methodologies and tools to handle the SoC codesign aspects. This paper presents a novel SoC co-design methodology based on Model Driven Engineering and the Modeling and Analysis of Real-Time and Embedded Systems (MARTE) standard, permitting us to raise the abstraction levels and allows to model fine grain reconfigurable architectures such as FPGAs. Extensions of this methodology have enabled us to integrate new features such as Partial Dynamic Reconfiguration supported by Modern FPGAs. The overall objective is to carry out system modeling at a high abstraction level expressed in a graphical language like Unified Modeling Language (UML) and afterwards transformation of these models automatically generate the necessary code for FPGA synthesis.