High level modeling of dynamic reconfigurable FPGAs
International Journal of Reconfigurable Computing - Selected papers from ReCoSoc08
INDEXYS*, a logical step beyond GENESYS
SAFECOMP'10 Proceedings of the 29th international conference on Computer safety, reliability, and security
Accurate Area, Time and Power Models for FPGA-Based Implementations
Journal of Signal Processing Systems
ASP-based optimized mapping in a simulink-to-MPSoC design flow
Journal of Systems Architecture: the EUROMICRO Journal
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The Scalable Communications Core (SCC) is a power- and area-efficient solution for physical layer (PHY) and lower MAC processing of concurrent multiple wireless protocols. Our architecture consists of coarse-grained, heterogeneous, programmable accelerators ...