Customized kernel execution on reconfigurable hardware for embedded applications
Microprocessors & Microsystems
High level modeling of dynamic reconfigurable FPGAs
International Journal of Reconfigurable Computing - Selected papers from ReCoSoc08
Slotless module-based reconfiguration of embedded FPGAs
ACM Transactions on Embedded Computing Systems (TECS)
Server-side coprocessor updating for mobile devices with FPGAs
Proceedings of the 18th annual ACM/SIGDA international symposium on Field programmable gate arrays
Improving flexibility in on-line evolvable systems by reconfigurable computing
ICES'07 Proceedings of the 7th international conference on Evolvable systems: from biology to hardware
Internal and external bitstream relocation for partial dynamic reconfiguration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Mechanism of resource virtualization in RCS for multitask stream applications
International Journal of Reconfigurable Computing - Special issue on selected papers from ReconFig 2009 International conference on reconfigurable computing and FPGAs (ReconFig 2009)
Architecture and operating system support for two-dimensional runtime partial reconfiguration
The Journal of Supercomputing
Achieving energy efficiency through runtime partial reconfiguration on reconfigurable systems
ACM Transactions on Embedded Computing Systems (TECS)
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Short time-to-market pressure, high cost and risks and power consumption are keywords in development of microelectronic solutions for embedded systems as well as for universal and application tailored processor architectures. Modularity and flexibility while designtime, e.g. for System-on-Chip (SoC) component design, is not sufficient if the possibility of run-time reconfiguration of novel architectures has to be considered. Here, exploitation of real-time and on-demand reconfiguration of silicon area personalized on suitable granularities demonstrates high situation adaptivity and perspectives for next generation microelectronics. This paper discusses our implemented, synthesized and tested ondemand and partial reconfiguration approaches for finegrain (Xilinx Virtex FPGAs) data paths. This includes also very new dynamic and partial reconfiguration for 2D placement and routing adaptation for today's fine-grain Xilinx FPGAs