Transistor sizing issues and tool for multi-threshold CMOS technology
DAC '97 Proceedings of the 34th annual Design Automation Conference
Distributed sleep transistor network for power reduction
Proceedings of the 40th annual Design Automation Conference
Understanding and minimizing ground bounce during mode transition of power gating structures
Proceedings of the 2003 international symposium on Low power electronics and design
An effective power mode transition technique in MTCMOS circuits
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 43rd annual Design Automation Conference
Sleep transistor sizing for leakage power minimization considering temporal correlation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Technique for controlling power-mode transition noise in distributed sleep transistor network
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
ACM Transactions on Architecture and Code Optimization (TACO)
Proceedings of the International Conference on Computer-Aided Design
Efficient on-line module-level wake-up scheduling for high performance multi-module designs
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
Power-up sequence control for MTCMOS designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Power gating in circuits is one of the effective technologies to allow low leakage and high performance operations. This work aims to analyze and establish the relations between the three important design parameters in power gated circuits: (i) the maximum current flowing from/to power/ground (ii) the wakeup (sleep to active mode transition) time delay and (iii) the number of sleep transistors. With the understanding of relations between the parameters, we propose solutions to the two problems: (1) finding logic clusters and their wakeup schedule to minimize the sleep transistor overhead under the constraints of wakeup time and peak current and (2) finding logic clusters and their wakeup schedule to minimize the wakeup time under the constraints of peak current and the number of sleep transistors. From an experimentation using ISCAS benchmarks, it is shown that our proposed technique is able to explore the search space, finding solutions with 65% ~ 77% reduced number of sleep transistors and 30% ~ 36% reduced wakeup time delay, compared to the results by the previous work.