Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Power minimization in IC design: principles and applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Automating RT-level operand isolation to minimize power consumption in datapaths
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
Low Power Digital CMOS Design
Controller-based power management for control-flow intensive designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Behavior-level observability don't-cares and application to low-power behavioral synthesis
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Behavior-Level Observability Analysis for Operation Gating in Low-Power Behavioral Synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Traditional RTL power optimization techniques committransformations at the RTL based on the estimation of area, delayand power. However, because of inadequate power and delayinformation, the power optimization transformations applied atthe RTL may cause unexpected results after synthesis, such asworsened delay or increased power dissipation. Our solution tothis problem is to divide RTL power optimization into two steps,namely RTL exploration and gate-level commitment. During RTLexploration phase potential candidates for applying some specificRTL transformation are identified where high level informationpermits faster and more effective analysis. These candidates aresimply "marked" on the netlist. Then during the gate-levelcommitment phase when accurate power and delay information isavailable, the final decision of whether accepting or rejecting thecandidate is made to achieve the best power and delay trade-offs.