Precomputation-based sequential logic optimization for low power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Common-case computation: a high-level technique for power and performance optimization
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Computers
Security Engineering: A Guide to Building Dependable Distributed Systems
Security Engineering: A Guide to Building Dependable Distributed Systems
Handbook of Applied Cryptography
Handbook of Applied Cryptography
Examining Smart-Card Security under the Threat of Power Analysis Attacks
IEEE Transactions on Computers
Power Analysis Attacks of Modular Exponentiation in Smartcards
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
Multiplicative Masking and Power Analysis of AES
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
Masking the Energy Behavior of DES Encryption
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Design principles for tamper-resistant smartcard processors
WOST'99 Proceedings of the USENIX Workshop on Smartcard Technology on USENIX Workshop on Smartcard Technology
Guarded evaluation: pushing power management to logic synthesis/design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Synthesis of power-managed sequential components based on computational kernel extraction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A novel architecture for power maskable arithmetic units
Proceedings of the 13th ACM Great Lakes symposium on VLSI
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Security as a new dimension in embedded system design
Proceedings of the 41st annual Design Automation Conference
Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Simulation models for side-channel information leaks
Proceedings of the 42nd annual Design Automation Conference
Current mask generation: a transistor level security against DPA attacks
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
IEEE Transactions on Dependable and Secure Computing
Dual-rail transition logic: A logic style for counteracting power analysis attacks
Computers and Electrical Engineering
Vulnerability modeling of cryptographic hardware to power analysis attacks
Integration, the VLSI Journal
Power analysis attacks on MDPL and DRSL implementations
ICISC'07 Proceedings of the 10th international conference on Information security and cryptology
An architecture-independent instruction shuffler to protect against side-channel attacks
ACM Transactions on Architecture and Code Optimization (TACO) - HIPEAC Papers
Three-phase dual-rail pre-charge logic
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
ICISC'05 Proceedings of the 8th international conference on Information Security and Cryptology
Power Analysis Attack Resistance Engineering by Dynamic Voltage and Frequency Scaling
ACM Transactions on Embedded Computing Systems (TECS)
POWER-MODES: POWer-EmulatoR- and MOdel-Based DEpendability and Security Evaluations
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
The schedulability of AES as a countermeasure against side channel attacks
SPACE'12 Proceedings of the Second international conference on Security, Privacy, and Applied Cryptography Engineering
A Comparative Survey on Cryptology-Based Methodologies
International Journal of Information Security and Privacy
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Differential power analysis is a very effective cryptanalysis technique that extracts information on secret keys by monitoring instantaneous power consumption of cryptoprocessors. To protect against differential power analysis, power supply noise is added in cryptographic computations, at the price of an increase in power consumption. We present a novel technique, based on well-known power-reducing transformations coupled with randomized clock gating, that introduces a significant amount of scrambling in the power profile without increasing (and, in some cases, by even reducing) circuit power consumption.