Energy-driven integrated hardware-software optimizations using SimplePower
Proceedings of the 27th annual international symposium on Computer architecture
Design issues for dynamic voltage scaling
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Applied Cryptography: Protocols, Algorithms, and Source Code in C
Applied Cryptography: Protocols, Algorithms, and Source Code in C
CRYPTO '99 Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology
ElectroMagnetic Analysis (EMA): Measures and Counter-Measures for Smart Cards
E-SMART '01 Proceedings of the International Conference on Research in Smart Cards: Smart Card Programming and Security
Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems
CRYPTO '96 Proceedings of the 16th Annual International Cryptology Conference on Advances in Cryptology
DES and Differential Power Analysis (The "Duplication" Method)
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
Resistance against Differential Power Analysis for Elliptic Curve Cryptosystems
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
Energy-aware design techniques for differential power analysis protection
Proceedings of the 40th annual Design Automation Conference
Improving Smart Card Security Using Self-Timed Circuits
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Embedding Security in Wireless Embedded Systems
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Cryptosystem Designed for Embedded System Security
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Energy-efficient data scrambling on memory-processor interfaces
Proceedings of the 2003 international symposium on Low power electronics and design
Low-Cost Solutions for Preventing Simple Side-Channel Analysis: Side-Channel Atomicity
IEEE Transactions on Computers
Off-chip latency-driven dynamic voltage and frequency scaling for an MPEG decoding
Proceedings of the 41st annual Design Automation Conference
Security as a new dimension in embedded system design
Proceedings of the 41st annual Design Automation Conference
Theoretical and practical limits of dynamic voltage scaling
Proceedings of the 41st annual Design Automation Conference
PACE: A New Approach to Dynamic Voltage Scaling
IEEE Transactions on Computers
Computer
An On-Chip Signal Suppression Countermeasure to Power Analysis Attacks
IEEE Transactions on Dependable and Secure Computing
ITNG '07 Proceedings of the International Conference on Information Technology
Design principles for tamper-resistant smartcard processors
WOST'99 Proceedings of the USENIX Workshop on Smartcard Technology on USENIX Workshop on Smartcard Technology
Power Attacks Resistance of Cryptographic S-boxes with added Error Detection Circuits
DFT '07 Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Defeating classical hardware countermeasures: a new processing for side channel analysis
Proceedings of the conference on Design, automation and test in Europe
Security Evaluation of WDDL and SecLib Countermeasures against Power Attacks
IEEE Transactions on Computers
Dynamic Voltage Scaling for Multitasking Real-Time Systems With Uncertain Execution Time
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This article proposes a novel approach to cryptosystem design to prevent power analysis attacks. Such attacks infer program behavior by continuously monitoring the power supply current going into the processor core. They form an important class of security attacks. Our approach is based on dynamic voltage and frequency scaling (DVFS), which hides processor state to make it harder for an attacker to gain access to a secure system. Three designs are studied to test the efficacy of the DVFS method against power analysis attacks. The advanced realization of our cryptosystem is presented which achieves enough high power and time trace entropies to block various kinds of power analysis attacks in the DES algorithm. We observed 27% energy reduction and 16% time overhead in these algorithms. Finally, DVFS hardness analysis is presented.