Precomputation-based sequential logic optimization for low power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Security Engineering: A Guide to Building Dependable Distributed Systems
Security Engineering: A Guide to Building Dependable Distributed Systems
Examining Smart-Card Security under the Threat of Power Analysis Attacks
IEEE Transactions on Computers
Energy-aware design techniques for differential power analysis protection
Proceedings of the 40th annual Design Automation Conference
Design principles for tamper-resistant smartcard processors
WOST'99 Proceedings of the USENIX Workshop on Smartcard Technology on USENIX Workshop on Smartcard Technology
Sequential logic optimization for low power using input-disabling precomputation architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Satisfiability-based framework for enabling side-channel attacks on cryptographic software
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
Aiding side-channel attacks on cryptographic software with satisfiability-based analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ICISC'05 Proceedings of the 8th international conference on Information Security and Cryptology
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Power maskable units have been proposed as a viable solution for preventing side-channel attacks to cryptoprocessors. This paper presents a novel architecture for the implementation of a class of such kinds of units, namely arithmetic components, which find wide usage in cryptographic applications and which are not suitable to traditional masking techniques. Results of extensive exploration and architectural trade-off analysis show the viability of the proposed solution.