Power estimation methods for sequential logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Evaluating Run-Time Techniques for Leakage Power Reduction
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Power Gating with Multiple Sleep Modes
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
A fast and elitist multiobjective genetic algorithm: NSGA-II
IEEE Transactions on Evolutionary Computation
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Zigzag power gating (ZPG) has been proposed to alleviate the drawback of power gating in its long wake-up delay, thereby broadening the application of power gating to suppressing active- as well as standby-leakage. However, complicated power network due to the use of nMOS and pMOS switches in zigzag fashion has limited its application to custom circuits. Heterogeneous use of power rails inevitably incurs overhead of area and wirelength during physical design. Furthermore, the use of sleep vector causes additional switching power when entering standby mode and returning back to active mode. The switching power should be minimized not to outweigh the leakage saving by employing ZPG scheme. In this paper, we propose a complete power network architecture, which allows us to use unmodified standard cell elements for implementing ZPG circuits. We formulate selecting sleep vector as a multi-objective optimization problem, minimizing transition energy and total wirelength. We solve the problem by employing multiobjective genetic-based algorithm. Experimental results show the saving of 39% in transition energy and 8% in wirelength, on average, for several benchmark circuits in 65-nm technology. The complete design flow starting from RTL description down to layout is proposed, and assessed with 65-nm technology.