Techniques for the power estimation of sequential logic circuits under user-specified input sequences and programs

  • Authors:
  • José Monteiro;Srinivas Devadas

  • Affiliations:
  • Department of EECS, MIT, Cambridge, MA;Department of EECS, MIT, Cambridge, MA

  • Venue:
  • ISLPED '95 Proceedings of the 1995 international symposium on Low power design
  • Year:
  • 1995

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Abstract