Power analysis for sequential circuits at logic level

  • Authors:
  • M. Senn;P. Schneider;B. Wurth

  • Affiliations:
  • Inst. of EDA, TU-Munich, D-81730 Munich;Siemens AG, ZFE T SE 5, D-81730 Munich and Inst. of EDA, TU-Munich, D-81730 Munich;Synopsys, Inc., 700 E. Middlefield Road, Mountain View, CA

  • Venue:
  • EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
  • Year:
  • 1996

Quantified Score

Hi-index 0.00

Visualization

Abstract