Partitioning Sequential Circuits for Logic Optimization

A unified cost model for min-cut partitioning with replication applied to optimization of large heterogeneous FPGA partitions

EURO-DAC '94 Proceedings of the conference on European design automation

Power analysis for sequential circuits at logic level

EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation

Using precomputation in architecture and logic resynthesis

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design

Optimization of synchronous circuits

Logic Synthesis and Verification

Retiming: Theory and practice

Integration, the VLSI Journal