Statistical estimation of sequential circuit activity
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Power analysis for sequential circuits at logic level
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
High-Performance Low-Power CMOS Circuits Using Multiple Channel Length and Multiple Oxide Thickness
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Low Power VLSI Design Techniques - The Current State
Integrated Computer-Aided Engineering
Power Estimation Under Uncertain Delays
Integrated Computer-Aided Engineering
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We present an exact and an approximate method for estimating signal activity at the internal nodes of sequential logic circuits. The methodology takes spatial and temporal correlations of logic signals into consideration. Given the state transition graph (STG) of a finite state machine (FSM), we create an extended state transition graph (ESTG), where the temporal correlations of the input signals are explicitly represented. From the graph we derive the equations to calculate exact signal probabilities and activities. For large circuits an approximate method for calculating the activities by unrolling the next state logic is proposed. Experimental results show that if temporal and spatial correlations are not considered, the switching activities of the internal nodes can be off by more than 40% compared to simulation based techniques. However, the results of the approximate method proposed in the paper is within 5% of logic simulation results.