Stochastic Neural Computation I: Computational Elements
IEEE Transactions on Computers
Test set enrichment using a probabilistic fault model and the theory of output deviations
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Functionally Fault-tolerant DSP Microprocessor using Sigma---delta Modulated Signals
Journal of Electronic Testing: Theory and Applications
The synthesis of robust polynomial arithmetic with stochastic logic
Proceedings of the 45th annual Design Automation Conference
Stochastic decoding of turbo codes
IEEE Transactions on Signal Processing
| Hi-index | 35.69 |
A space-efficient fully parallel stochastic computation architecture is described. It circumvents the main drawback of stochastic computation architectures that have been used up to now: the absence of a space-efficient technique of adding weighted input signals in parallel