Bisimulation through probabilistic testing
Information and Computation
1995 high level synthesis design repository
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Symbolic execution and program testing
Communications of the ACM
POPL '77 Proceedings of the 4th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
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PAPM-PROBMIV '01 Proceedings of the Joint International Workshop on Process Algebra and Probabilistic Methods, Performance Modeling and Verification
Program Slicing of Hardware Description Languages
CHARME '99 Proceedings of the 10th IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods
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CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Automated Verification of a Randomized Distributed Consensus Protocol Using Cadence SMV and PRISM
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
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ICCD '98 Proceedings of the International Conference on Computer Design
Optimal state-space lumping in Markov chains
Information Processing Letters
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
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DSN '04 Proceedings of the 2004 International Conference on Dependable Systems and Networks
PRISM 2.0: A Tool for Probabilistic Model Checking
QEST '04 Proceedings of the The Quantitative Evaluation of Systems, First International Conference
Probability and Computing: Randomized Algorithms and Probabilistic Analysis
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Tutorial II: Variability and Its Impact on Design
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
NBTI-aware synthesis of digital circuits
Proceedings of the 44th annual Design Automation Conference
Game-Based Probabilistic Predicate Abstraction in PRISM
Electronic Notes in Theoretical Computer Science (ENTCS)
Abstraction Refinement for Probabilistic Software
VMCAI '09 Proceedings of the 10th International Conference on Verification, Model Checking, and Abstract Interpretation
DynaTune: circuit-level optimization for timing speculation considering dynamic path behavior
Proceedings of the 2009 International Conference on Computer-Aided Design
A minimalistic look at widening operators
Higher-Order and Symbolic Computation
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ZB'03 Proceedings of the 3rd international conference on Formal specification and development in Z and B
Magnifying-lens abstraction for Markov decision processes
CAV'07 Proceedings of the 19th international conference on Computer aided verification
Automatic Compositional Reasoning for Probabilistic Model Checking of Hardware Designs
QEST '10 Proceedings of the 2010 Seventh International Conference on the Quantitative Evaluation of Systems
Variation-Conscious Formal Timing Verification in RTL
VLSID '11 Proceedings of the 2011 24th International Conference on VLSI Design
Advances in probabilistic model checking
VMCAI'10 Proceedings of the 11th international conference on Verification, Model Checking, and Abstract Interpretation
Symmetry reduction for probabilistic model checking
CAV'06 Proceedings of the 18th international conference on Computer Aided Verification
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Sources of randomness such as physical process variations and input pattern variations make hardware timing a statistical measure. It is desirable to verify statistical timing properties at the higher levels of design such as the Register Transfer Level (RTL). The RTL design can be modeled as a Discrete Time Markov Chain (DTMC) and probabilistic model checking then applied to verify that the DTMC satisfies a desired timing specification. However, we find that such an approach does not scale beyond 1010 states. In this paper, we introduce an abstraction methodology to scale this approach to large designs. Instead of considering the entire space of data values that can be assigned to the design input variables, we perform a value-based interval abstraction by considering only those intervals of input values that are relevant to a given timing property. We employ symbolic execution on the RTL source code to automatically derive such intervals for the design inputs, with respect to a given timing property. We use these intervals to construct smaller abstract DTMCs and thereby make the corresponding probabilistic model checking problems more tractable. We show that our abstraction is sound since we do not remove any probabilistic behavior that is relevant to the property of interest. We demonstrate the effectiveness of our technique using multiple designs used in communication systems such as FFT, filters and several modules of a real world H.264 decoder. We use our technique to successfully verify timing of an H.264 module, for which the concrete model contains more that 1080 states, by constructing an abstract model with approximately only 1010 states.