Low-leakage asymmetric-cell SRAM
Proceedings of the 2002 international symposium on Low power electronics and design
Resistance Characterization for Weak Open Defects
IEEE Design & Test
The Effect of Threshold Voltages on the Soft Error Rate
ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Characterization of Soft Errors Caused by Single Event Upsets in CMOS Processes
IEEE Transactions on Dependable and Secure Computing
Soft Errors in Advanced Computer Systems
IEEE Design & Test
Analytical modeling of SRAM dynamic stability
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Analysis and optimization of nanometer CMOS circuits for soft-error tolerance
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design hardening of nanometer SRAMs through transistor width modulation and multi-Vt combination
IEEE Transactions on Circuits and Systems II: Express Briefs
Reliable on-chip systems in the nano-era: lessons learnt and future trends
Proceedings of the 50th Annual Design Automation Conference
An infrastructure for accurate characterization of single-event transients in digital circuits
Microprocessors & Microsystems
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Scaling transistor size to the scale of the nanometer coupled with reduction of supply voltage has made SRAMs more vulnerable to soft errors than ever before. The vulnerability has been accentuated by increased variability in device parameters. In this paper, we present an analytical model for critical charge in order to assess the soft error vulnerability of 6T SRAM cell. The model takes into account the dynamic behavior of the cell and demonstrates a simple technique to decouple the nonlinearly coupled storage nodes. Decoupling of storage nodes enables solving associated current equations to determine the critical charge for an exponential noise current. The critical charge model thus developed consists of both NMOS and PMOS transistor parameters. Consequently, the model can estimate critical charge variations due to variability of transistor parameters and manufacturing defects, such as resistive contacts and vias. In addition, the model can serve as a tool to optimize the hibernation voltage of low-power SRAMs or the size ofMIMcapacitor per cell in order to achieve a target soft error robustness. Critical charge calculated by the model is in good agreement with SPICE simulations for a commercial 90-nmCMOS process with a maximum discrepancy of less than 5%.