The use of observability and external don't cares for the simplification of multi-level networks
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A new method to express functional permissibilities for LUT based FPGAs and its applications
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A re-engineering approach to low power FPGA design using SPFD
DAC '98 Proceedings of the 35th annual Design Automation Conference
Implementation and use of SPFDs in optimizing Boolean networks
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
A new enhanced SPFD rewiring algorithm
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Enhancing design robustness with reliability-aware resynthesis and logic simulation
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Robust FPGA resynthesis based on fault-tolerant Boolean matching
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Architecture Design for Soft Errors
Architecture Design for Soft Errors
IPR: in-place reconfiguration for FPGA fault tolerance?
Proceedings of the 2009 International Conference on Computer-Aided Design
Fault-tolerant resynthesis with dual-output LUTs
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Design of robust metabolic pathways
Proceedings of the 48th Design Automation Conference
Mitigating FPGA interconnect soft errors by in-place LUT inversion
Proceedings of the International Conference on Computer-Aided Design
On power and fault-tolerance optimization in FPGA physical synthesis
Proceedings of the International Conference on Computer-Aided Design
SEU fault evaluation and characteristics for SRAM-based FPGA architectures and synthesis algorithms
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
Retiming for Soft Error Minimization Under Error-Latching Window Constraints
Proceedings of the Conference on Design, Automation and Test in Europe
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Logic synthesis for soft error mitigation is increasingly important in a wide range of applications of FPGAs. We present R2, an algorithm for rewiring a post-layout LUT-based circuit that reduces the overall criticality of the circuit, where criticality is the fraction of primary inputs that lead to observable errors at the primary outputs if an single event upset inverts a configuration bit. Our algorithm explicitly optimizes the robustness of the interconnect, the dominant component of FPGAs. The key idea of R2 is to exploit Boolean flexibilities in the circuit implementation to replace wires with high criticality with those with lower criticality while preserving the circuit functionality. We estimate criticalities using a Monte Carlo fault simulation. We represent flexibilities using SPFDs (Set of Pairs of Functions to be Distinguished), and use criticality information to choose candidates for rewiring, assigning the maximum flexibility to high criticality wires. Compared to IPR, a recent robust logic optimization, our implementation increases MTTF (Mean Time to Failure) by 24%, showing for the first time, the advantages of exploiting Boolean flexibilities in optimizing for robustness. In addition, R2 achieves 5% and 2% more reduction on the number of wires and LUTs in an FPGA than that obtained by the existing rewiring algorithm for area minimization.