Implementation of BEE: a real-time large-scale hardware emulation engine

Authors:
Chen Chang;Kimmo Kuusilinna;Brian Richards;Robert W. Brodersen
Affiliations:
University of California, Berkeley, Berkeley, CA;University of California, Berkeley, Berkeley, CA, and Tampere University of Technology, Tampere, Finland;University of California, Berkeley, Berkeley, CA;University of California, Berkeley, Berkeley, CA
Venue:
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Year:
2003

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Abstract

This paper describes the hardware implementation of a real-time, large-scale, multi-chip FPGA (Field Programmable Gate Array) based emulation engine with a capacity of 10 million ASIC (Application Specific Integrated Circuits) equivalent gates. Attainable system operation frequency can exceed 60 MHz, and the system throughput has been empirically verified to achieve 600 billion 16-bit additions per second. The emulator is custom designed to maximize the performance and resource utilization for a range of telecommunication and digital signal processing applications. With its high-speed interconnect architecture and large external I/O bandwidth, the emulator excels in prototyping real-time systems that have strict timing, logic capacity, and data rate requirements. Our development efforts are guided by such ongoing projects as ultra-wide band (UWB) and multi-channel-multi-antenna (MCMA) radio systems research.