A new simultaneous circuit partitioning and chip placement approach based on simulated annealing
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A matrix synthesis approach to thermal placement
Proceedings of the 1997 international symposium on Physical design
Algorithms for VLSI Physical Design Automation
Algorithms for VLSI Physical Design Automation
Thermal placement for high-performance multichip modules
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
A combined force and cut algorithm for hierarchical VLSI layout
DAC '82 Proceedings of the 19th Design Automation Conference
Object-Oriented Thermal Placement Using an Accurate Heat Model
HICSS '99 Proceedings of the Thirty-Second Annual Hawaii International Conference on System Sciences-Volume 3 - Volume 3
Mcg: a multilayer general area mcm routing algorithm
Mcg: a multilayer general area mcm routing algorithm
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Typically, placement algorithms attempt to minimize the total net length of a printed circuit board (PCB). However, an MCM's increased throughput and dense circuitry can easily result in failure if the board contains “hot spots”. Therefore, an accurate thermal model of an MCM was needed in the development of a new placement algorithm designed to consider both total net length and thermal constraints. This algorithm uses a combination of simulated evolution and simulated annealing in an iterative approach. Each chip has a maximum thermal tolerance that it can withstand before it is known to fail. The fitness method evaluates the maximum temperature for each chip, considering every chip's thermal dissipation at the chip's hottest point. Results are presented that compare the effects of various parameters.