Simulated annealing for VLSI design
Simulated annealing for VLSI design
A digit-serial silicon compiler
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
MCM placement using a realistic thermal model
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
A Rapid-Prototyping Environment for Digital-Signal Processors
IEEE Design & Test
Evolutionary and adaptive synthesis methods
Formal engineering design synthesis
Lock-Gain Based Graph Partitioning
Journal of Heuristics
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The problems of circuit partitioning and chip placement have been studied in the past. Given a circuit partitioned into chips, one can optimize the placement of the chips on a printed circuit board with regard to a given cost function. Conversely, given a placement of the chips on the board, one can optimize the partitioning of the circuit into the chips with regard to the same cost function. However, given neither the circuit partitioning nor the chip placement, we are faced with a difficult optimization problem. Our target technology is one in which the chips are unpackaged chips placed on a substrate, analogous to the printed circuit board and interconnected together with high density interconnect to realize a complex system. We propose a new approach in which the circuit is both partitioned and placed simultaneously by a simulated annealing based algorithm. Our approach is seen to yield excellent results in reasonable run times.