A digit-serial silicon compiler

Authors:
Richard I. Hartley;Peter F. Corbett
Affiliations:
General Electric R&D Center, Schenectady, NY;General Electric R&D Center, Schenectady, NY
Venue:
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Year:
1988

Citing 2
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Abstract

A new silicon compiler is described, called PARSIFAL (not an acronym). It constructs chips with a data flow architecture in which data is passed in a digit-wide pipeline from one computational element to the next. The size of a digit may be specified by the user to be any value between one and the full word size of the chip. A digit size of one gives bit-serial chips whereas a digit-size equal to the word-size gives fully parallel computation. It is shown that an intermediate value of digit-size usually gives the most efficient chips in terms of throughput per unit area.