Interconnection synthesis with geometric constraints

Authors:
Forrest Brewer;Barry Pangrle;Andrew Seawright
Affiliations:
ECE Dept., University of California, Santa Barbara, CA and CS Dept., Pennsylvania State University, University Park, PA;ECE Dept., University of California, Santa Barbara, CA and CS Dept., Pennsylvania State University, University Park, PA;ECE Dept., University of California, Santa Barbara, CA and CS Dept., Pennsylvania State University, University Park, PA
Venue:
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
Year:
1990

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Abstract

We describe a simple linear placement model applicable to bit-slice data-paths and to the simultaneous generation of geometric layout with the synthesis of the interconnection nets required for communication. This model allows direct area trade-offs between several alternative interconnection devices such as multiplexers, busses, tri-state drivers and point-to-point wire connections. Addition of geometric constraints to the interconnection synthesis allows accurate interpretation of the designed connections in terms of the actual area required and the relative speed and routing limitations. Use of direct area cost functions in the design of the interconnections leads to different designs than do the a priori cost functions commonly used in high level synthesis systems. The newer designs make better use of the area and routing density than do designs where previously minimized interconnections are mapped into a linear placement. Also described is a new fast heuristic for linear placement which is used interactively as a cost function in the interconnection design.