Memory, control and communications synthesis for scheduled algorithms

Authors:
Douglas M. Grant;Peter B. Denyer
Affiliations:
Silicon Architectures Research Initiative, Department of Electrical Engineering, University of Edinburgh, Scotland, EH9 3JL;Silicon Architectures Research Initiative, Department of Electrical Engineering, University of Edinburgh, Scotland, EH9 3JL
Venue:
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Year:
1991

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Abstract

This paper explores a method of grouping individual memory requirements from a hardware-constrained schedule of an algorithm, such that control and communications may be optimised. A new representation of memory requirements is introduced to explain the method. The technique may also be used to allocate operations to hardware resources. This, and control and communication optimisation are illustrated with an example.