Simulated annealing and Boltzmann machines: a stochastic approach to combinatorial optimization and neural computing
Wire routing by optimizing channel assignment within large apertures
DAC '71 Proceedings of the 8th Design Automation Workshop
A class of min-cut placement algorithms
DAC '77 Proceedings of the 14th Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Gate matrix is a layout style for implementing logic in integrated MOS circuits. In this paper we discuss algorithms used in a newly developed software package called PARAGON which generates near-optimal gate matrix geometric layouts given a set of logic expressions. New features include individual sizes of transistors being taken into account at all stages of the algorithms and the use of transistor orientations to reduce the width and improve the timing performance of the gate matrix layouts. The optimisation of a gate matrix is achieved by optimising firstly its height and secondly its width. The height is optimised by the column assignment algorithm and the width is optimised by the merging, track assignment and transistor orientation algorithms. Once optimisation has been completed, a new detailed routing algorithm is performed. Although the emphasis is on the minimisation of the total area, the optimisation of the timing behaviour is also included in our algorithms.