NES: the behavioral model for the formal semantics of a hardware design language UDL/I

Authors:
Nagisa Ishiura;Hiroto Yasuura;Shuzo Yajima
Affiliations:
Department of Information Science, Faculty of Engineering, Kyoto University, Kyoto 606, JAPAN;Department of Electronics, Faculty of Engineering, Kyoto University, Kyoto 606, JAPAN;Department of Information Science, Faculty of Engineering, Kyoto University, Kyoto 606, JAPAN
Venue:
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Year:
1991

Citing 5
Cited 0

VLSI design language standardization effort in Japan

DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Semantics of a hardware design language for Japanese standardization

DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Coded time-symbolic simulation using shared binary decision diagram

DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
The VHDL Handbook

The VHDL Handbook
CONLAN Report

CONLAN Report

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper describes a new behavioral model of hardware, named NES (Nondeterministic Event Sequence) model, which was developed for the purpose of defining formal semantics of the gate level and the register transfer level hardware description languages. The NES model is a generalization of the event driven simulation, and can be a basis of synthesis and verification as well as simulation. We introduce basic concepts, formal definition, and a description method of the NES model.