Verification of VHDL designs using VAL

Authors:
Larry M. Augustin;Benoit A. Gennart;Youm Huh;David C. Luckham;Alec G. Stanculescu
Affiliations:
Computer Systems Laboratory, Stanford University, Stanford, California;Computer Systems Laboratory, Stanford University, Stanford, California;Computer Systems Laboratory, Stanford University, Stanford, California;Computer Systems Laboratory, Stanford University, Stanford, California;Computer Systems Laboratory, Stanford University, Stanford, California
Venue:
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Year:
1988

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Abstract

VAL (VHDL Annotation Language) uses a small number of new language constructs to annotate VHDL hardware descriptions. VAL annotations, added to the VHDL entity declaration in the form of formal comments, express intended behavior common to all architectural bodies of the entity. Annotations are expressed as parallel processes that accept streams of input signals and generate constraints on output streams. VAL views signals as streams of values ordered by time. Generalized timing expressions allow the designer to refer to relative points on a stream. No concept of preemptive delayed assignment or inertial delay are needed when referring to different relative points in time on a stream. The VAL abstract state model permits abstract data types to be used in specifying history dependent device behavior. Annotations placed inside a VHDL architectural body define detailed correspondences between the behavior specification and architecture. The result is a simple but expressive language extension of VHDL with possible applications to automatic checking of VHDL simulations, hierarchical design, and automatic verification of hardware designs in VHDL.