VVDS: a verification/diagnosis system for VHDL

Authors:
H. T. Liaw;K.-T. Tran;C.-S. Lin
Affiliations:
Department of Electrical Engeneering, National Taiwan University, Taipei, Taiwan, ROC;Department of Electrical Engeneering, National Taiwan University, Taipei, Taiwan, ROC;Department of Electrical Engeneering, National Taiwan University, Taipei, Taiwan, ROC
Venue:
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Year:
1989

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Abstract

In this paper, an interactive verification and diagnosis system for VHDL [Vm88], VVDS, is presented. In VVDS, hybrid simulation, which simulates with both numerical and symbolic data, is implemented to achieve an effective compromise of the enormous quantity of input test data in the conventional simulation and the complexity of symbolic expression in the symbolic execution. To support efficient user interface in the verification and diagnosis process, both on-line programming of commands and micro-probing capability to passively and actively probe any level of design hierarchy are provided.