A computational logic handbook
A computational logic handbook
Parallel program design: a foundation
Parallel program design: a foundation
Formal Verification of VHDL Descriptions in the Prevail Environment
IEEE Design & Test
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To guarantee the correctness of hardware/software systems, formal verification provides an alternative approach to methods such as test or simulation. We are developing a proof environment, called PREVAIL, which is to support several input languages (currently, only VHDL is supported) and which proposes a set of proof tools to verify appropriate descriptions/specifications. In particular, we are working at defining an induction-based method to validate concurrent systems. To give such systems a formal specification, our first task was to choose between VHDL and a formal language that can be of interest to hardware/software developers. Using a reactive system as running example, we give a comparative evaluation of VHDL, LOTOS and UNITY. We draw conclusions about the accuracy of each one of them w.r.t. different aspects (sequential behaviours, communications, non determinism, fairness,...).